JEDEC-Compatible DQ/DQS Buffering for High-Capacity Load-Reduced DIMMs
The Deep-I DDRx Data Buffer (DB) is a JEDEC DDR5DB-compliant bidirectional data buffer designed for DDR5 and DDR4 LRDIMM applications. The DB isolates the DQ/DQS data path so the host memory controller does not directly see the large aggregate capacitive load of multiple DRAM devices and ranks. A DDR5 LRDIMM is equipped with one RCD and 10 DBs (5 per subchannel), each featuring a dual 4-bit host bus interface and a dual 4-bit DRAM interface connecting to two x4 DRAMs, enabling higher memory capacity, robust signal integrity, and maximized channel eye opening through capacitive load reduction, data alignment, and signal recovery.
Bidirectional DQ/DQS data buffer isolating host IMC from DRAM loading,
controlled by RCD via BCOM sideband bus for coordinated LRDIMM operation.
Dual 4-bit bidirectional host bus with DQS strobes. VDD-terminated drivers present controlled impedance to host IMC.
Host InterfaceDual 4-bit interface to two x4 DRAMs per DB. DQS regeneration and capacitive load reduction for max speed.
DRAM InterfaceData alignment and DFE on both host and DRAM interfaces maximize eye opening at high data rates.
EqualizationBCOM sideband from RCD for coordinated control. Dedicated ZQ calibration and parity error alert.
Sideband Control10 Data Buffers isolate DQ/DQS between host IMC and DRAM ranks for maximum capacity and signal integrity
Si-proven data buffer chip enabling 2× capacity over RDIMM with maximum speed
Enables 2× memory capacity vs RDIMM by isolating DRAM loading for higher density without signal degradation.
Load reduction, data alignment, and signal recovery maximize eye opening at full speed.
JEDEC DDR5DB01 compliant. Real Silicon verified. Optimized RCD/PMIC/SPD interoperability.
Advanced bidirectional buffering with coordinated RCD sideband control
Differential DQS strobes sample DQ inputs and are regenerated for driving the opposite side. DFE on both host and DRAM interfaces enables data rates beyond 9600 MT/s.
BCK/BCS_n/BCOM[3:0] sideband bus from RCD coordinates DB operating modes: normal, training, power-down, and loopback. BCKE and BODT pins for clock enable and on-die termination control.
Dedicated ZQ calibration pins for impedance matching. Parity error alert support for data-path reliability. Internal control word registers for flexible device configuration.
Si-proven DB chip portfolio for DDR4 through next-gen DDR5/DDR6 LRDIMM and MRDIMM.
First-gen DDR5 data buffer for mainstream LRDIMM. JEDEC DDR5DB01 compliant with DQS regeneration at 4800–6400 MT/s.
High-performance DDR5 data buffer for current-gen LRDIMM at 8800 MT/s with VDD-terminated drivers and DFE signal recovery.
Industry-leading DDR5 data buffer at 9600 MT/s with dual-side DFE and BCOM sideband for next-gen server LRDIMM.
Multiplexed Data Buffer for DDR5 MRDIMM targeting 12800+ MT/s. 2× bandwidth via dual-rank interleaving.
DDR5 Data Buffer chip portfolio at a glance
Speed grade evolution from DB01 to MDB
Deep-I DB is designed, verified, and characterized for first-time-right LRDIMM integration.
DDR5DB01 standard analysis. DQ/DQS interface, BCOM protocol, ZQ calibration, RCD coordination.
VDD-terminated drivers, DQS regeneration, DFE equalization, ZQ impedance calibration.
BCOM receiver integration, control registers, optimized 10-DB LRDIMM layout with SI/PI.
Real-Si fabrication. RCD+DB chipset validation, LRDIMM characterization, multi-vendor DRAM compatibility.
From JEDEC specification to Si-proven Data Buffer — see Deep-I's DB in action.
Contact our technical team to discuss your LRDIMM requirements and discover how Deep-I's JEDEC-compatible DB can accelerate your high-capacity server memory development.