Die-to-Die (D2D) I/F Solutions

High-Speed, Si-Proven On-Chip Interface for Multi-Die Systems

The Deep-I Die-to-Die (D2D) I/F solutions enables on-chip I/F logic to provide more reliable and high-speed solutions that enables higher performance and data reliability. The Deep-I Die-to-Die (D2D) I/F solutions are all Si-proven and mature memory interface solution in advanced process nodes.

36 Gb/sMax Data Rate
18 Gb/sStandard Rate
Bi-DirClock & Data
BISTBuilt-In Self-Test
CRC/ECCData Correction
Si-ProvenVerified Design
-40~125°CIndustrial Temp
Glass/OrgSubstrate Support
36 Gb/sMax Data Rate
18 Gb/sStandard Rate
Bi-DirClock & Data
BISTBuilt-In Self-Test
CRC/ECCData Correction
Si-ProvenVerified Design
-40~125°CIndustrial Temp
Glass/OrgSubstrate Support

Deep-I D2D I/F Solutions

State-of-the-art I/O transmitter (TX) and receiver (RX) circuit macro
supporting 3 Gb/s to 36 Gb/s per data wire on glass or organic substrates.

TX Circuit

1-bit or n-bit wire interface supporting 3 Gb/s to 36 Gb/s per data wire. TX clock uses differential signaling, TX data uses single-ended signaling. Low-jitter on-chip PLL provides reliable internal clock and forwards clock to point-to-point or multi-drop RXs.

Transmitter IP

RX Circuit

1-bit or n-bit wire interface supporting 3 to 36 Gb/s per data wire. Automatic BIST operation at initialization by on-chip auto read/write leveling and DQS de-skewing timing digital calibration for reliable RX analog clock and data lanes.

Receiver IP

BIST Circuit

Both RX and TX circuits provide automatic built-in self-test (BIST) pattern generation and self-checking for the complete data path through a TX/RX byte group. Per-DQ and Per-DQS BIST supports various PRBS data patterns.

Self-Test IP

Clocking Circuit

Clock RX receives 100 MHz reference clock input and provides low-power, high-speed differential clock output signal. Uses high-speed differential forwarded clock from TX group to sample data correctly.

Clock IP

D2D I/F System Architecture

Complete die-to-die interface from TX to RX across glass or organic interposer

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Key Benefits

Si-proven, high-speed die-to-die interface for multi-chip systems

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High Performance

18 Gb/s and 36 Gb/s I/F design provides unidirectional or bi-directional clock and data bandwidth for maximum throughput.

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Cost Effective

Provide our valuable multi-chip module on glass or organic substrates for cost-optimized multi-die integration.

Ultra-Low Latency

SI/PI (Signal and Power Integrity) analyzed, designed, verified for AI-powered applications requiring minimal latency overhead.

Key Features

Advanced mixed-signal architecture with built-in reliability

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On-Chip BIST & Calibration

Built-in self-test features for SI/PI-proven data reliability. On-chip read-write leveling, per-DQ de-skewing, and timing calibration.

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CRC/ECC Data Correction

Optional CRC/ECC data correction features for system reliability. Professional RDL routing and easy co-integration.

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Industrial Temperature Range

Full -40°C to 125°C industrial temperature range support with high-performance mixed-signal architecture for compact, low-power solutions.

Product Comparison

Compare key specifications across our D2D I/F portfolio

D2D I/F Solutions Comparison

Key specifications at a glance

Specification
D2D 36G
D2D 18G
TX/RX Macro
Clocking IP
Data Rate
36 Gb/s
18 Gb/s
3 ~ 36 Gb/s
Direction
Uni / Bi-dir
Uni / Bi-dir
Configurable
Forwarded CLK
Signaling
Diff CLK, SE Data
Diff CLK, SE Data
Diff CLK, SE Data
Differential
BIST
Per-DQ/DQS PRBS
Per-DQ/DQS PRBS
Per-DQ/DQS PRBS
ECC/CRC
Optional
Optional
Optional
Temperature
-40°C ~ +125°C
-40°C ~ +125°C
-40°C ~ +125°C
-40°C ~ +125°C
Si-Proven
✔ Yes
✔ Yes
✔ Yes
✔ Yes

From Concept to Si-Proven D2D

Deep-I D2D I/F solutions are analyzed, designed, and verified by real Silicon for reliable multi-die integration.

Phase 1

D2D Specification & Architecture

Define data-rate targets (3~36 Gb/s), signaling type (differential CLK, single-ended data), and multi-chip topology for glass or organic substrate.

Phase 2

TX/RX & PLL Circuit Design

High-performance mixed-signal (analog/digital) TX/RX macro design with low-jitter on-chip PLL, BIST pattern generation, and CRC/ECC data correction features.

Phase 3

SI/PI Verification & RDL Routing

Signal and power integrity analysis for point-to-point and multi-drop topologies. Professional RDL routing optimization for easy co-integration.

Phase 4

Silicon Fabrication & BIST Validation

Real-Si fabrication with automatic BIST validation at initialization. Per-DQ and per-DQS testing with PRBS patterns across -40°C to +125°C industrial range.

Visualize Your Idea

From concept to real-Silicon D2D integration — see Deep-I's D2D I/F solutions in action.

Ready to Integrate D2D I/F IP?

Contact our technical team to discuss your requirements and discover how Deep-I's D2D I/F solutions can accelerate your multi-die system development.