LPDDR6/5X/5/4X & DDR5 PHY — The Physical Layer Between Memory Controller and DRAM
The Deep-I PHY Interface IP is the critical physical layer connecting the SoC memory controller to DRAM devices. Supporting LPDDR6 at 14.4 Gb/s per pin (JEDEC JESD209-6, published July 2025), LPDDR5X at 10.7 Gb/s, and DDR5 at 9.6 Gb/s, the PHY delivers advanced equalization (DFE + FFE + CTLE), ultra-low-jitter DLL/PLL clock architecture, per-bit read/write delay calibration, and WCK (Write Clock) forwarding — all optimized for AI, HPC, mobile, automotive, and edge SoC applications. ISSCC 2026 validated: SK Hynix demonstrated 14.4 Gb/s/pin LPDDR6 at 1.025V with 20% power reduction and 50% bandwidth increase over LPDDR5.
Mixed-signal PHY with TX driver, RX receiver, triple equalization, WCK clock forwarding,
per-bit calibration, impedance control, and on-chip BIST — the bridge between controller and DRAM.
High-speed TX output driver with programmable impedance (ZQ calibration), slew-rate control, and Feed-Forward Equalization (FFE) pre-emphasis. Differential WCK clock driver for forwarded clock architecture (CKR 2:1 for LPDDR6). On-die termination (ODT) with dynamic NT-ODT adjustment based on operational demands.
TransmitterHigh-sensitivity RX input with Continuous-Time Linear Equalization (CTLE) pre-filter and multi-tap Decision Feedback Equalization (DFE). Per-pin DFE for LPDDR5X/6 enabling per-bit signal recovery. VREF training with programmable voltage reference for optimal sampling.
ReceiverUltra-low-jitter DLL/PLL clock architecture with duty-cycle correction. WCK (Write Clock) forwarded clock system with WCK LDO regulator reducing jitter by 30% (ISSCC 2026). Multi-phase clock generation for per-bit phase interpolator (PI) delay adjustment.
ClockingPer-bit read/write delay adjustment with fine-grain delay tuning. ZQ impedance calibration, read/write leveling, gate training, VREF training, and CA training. On-chip BIST with PRBS pattern generation for SI/PI-proven data reliability. DVFS/DVFSL support for dynamic power scaling.
Training EngineComplete physical layer from SoC memory controller DFI interface to LPDDR6/5X/DDR5 DRAM I/O
Si-proven PHY IP for AI, mobile, automotive, and HPC SoC applications
Industry-leading data rate supporting JEDEC LPDDR6 (JESD209-6, July 2025) at 14.4 Gb/s/pin with 48-bit data width, dual-subchannel-per-die architecture, and 50% bandwidth increase over LPDDR5.
Dual VDD2 supply (1.025V VDD2C, 0.875V VDD2D) achieving 20% power savings vs LPDDR5 (ISSCC 2026). DVFS/DVFSL dynamic scaling, clock gating, and advanced low-power training modes.
Combined DFE + FFE + CTLE equalization architecture for maximum eye opening at ultra-high speeds. Per-pin DFE enables per-bit signal recovery across variable system conditions.
ISSCC 2025/2026 validated circuit innovations for next-generation memory PHY
Common WCK LDO regulator reducing jitter by 30% (ISSCC 2026). Event-driven internal oscillator prevents overshoot. CKR 2:1 clock-to-write-clock ratio for LPDDR6 with ultra-low-jitter DLL.
Per-bit read and write delay adjustment with fine-grain PI (phase interpolator) tuning. Gate training, read/write leveling, VREF training, CA training, and ZQ impedance calibration.
LPDDR6 PRAC (per-row activation counting), programmable link protection, on-die ECC, error scrubbing, CA parity, MBIST, and dynamic NT-ODT for data integrity in AI/data center environments.
Si-proven PHY portfolio from LPDDR4X through next-generation LPDDR6 for every application.
Industry-first LPDDR6/5X dual-mode PHY supporting 14.4 Gb/s (LPDDR6) and 10.7 Gb/s (LPDDR5X). Triple EQ (DFE+FFE+CTLE), WCK LDO, 48-bit LPDDR6 data width, per-bit calibration, and CAMM2 support.
Si-proven LPDDR5X/5 PHY at 8533 Mb/s with per-pin DFE, WCK 4:1/2:1 forwarded clock, dual-channel architecture, and DVFS support for mobile/automotive/edge AI.
Mature, Si-proven LPDDR4X/4 PHY for cost-sensitive, high-volume mobile, consumer, IoT, and automotive applications with ultra-low power and compact area.
DDR5 PHY interface for server/HPC SoC integration, supporting up to 9600 MT/s with DFE, per-bit de-skew, and DFI 5.0 controller interface for RDIMM/UDIMM compatibility.
Compare specifications across our PHY interface portfolio
Key specifications at a glance
Mixed-signal PHY design, verification, and characterization across multiple process nodes.
LPDDR6 JESD209-6 / LPDDR5X JESD209-5C analysis. Define TX/RX architecture, equalization strategy (DFE+FFE+CTLE), WCK clock topology (CKR 2:1), data width (48-bit for LPDDR6), and DFI controller interface specification.
TX driver with FFE pre-emphasis and impedance control. RX with CTLE + multi-tap DFE. Ultra-low-jitter DLL/PLL with WCK LDO (30% jitter reduction). Phase interpolator for per-bit delay adjustment. ZQ calibration and VREF generator design.
Hardened PHY macro layout for target process node (7nm/5nm/4nm). On-chip training engine: read/write leveling, gate training, CA training, VREF training. BIST with PRBS patterns for SI/PI verification. Package/PCB co-design for bump map optimization.
Multi-node silicon bring-up with LPDDR6/5X DRAM. Eye diagram characterization at 14.4 Gb/s with margin reporting. DVFS/DVFSL power mode validation. Temperature/voltage shmoo across -40°C to +105°C. Complete PPA (power, performance, area) report.
From architecture to silicon — ultra-high-speed memory PHY delivering 14.4 Gb/s per pin.
Contact our team to discuss your SoC memory subsystem requirements — from LPDDR4X mobile to LPDDR6 AI data center — and discover how Deep-I's PHY IP can maximize your bandwidth while minimizing power.