We make memory
talk faster
Ultra-fast memory interfaces for the DDR5/6 · HBM era — proven in silicon.
The server DIMM
is our playground
Every signal path on an LRDIMM — RCD and data buffers — is our research target.
RCD — the chip that
re-drives the clock
Receives weakened clock/command and re-drives it to dozens of DRAMs. 9600+ MT/s, silicon-verified.
Hiding the load —
the Data Buffer
The controller never feels dozens of DRAMs — signals are regenerated and relaunched.
If the eye is open,
the data survives
The eye diagram is the health record of a link. Eye opening is design skill, made visible.
Reopening
a closed eye
CTLE and DFE undo what the channel destroyed — shown in waveforms, not equations.
Building clocks that
fight for picoseconds
PLL · DLL · Phase Interpolator — where one picosecond of jitter decides everything.
50Ω stays 50Ω,
whatever the weather
ZQ calibration holds the output impedance steady across PVT corners.
Keeping analog alive
below one volt
Analog gets harder as supplies shrink — we push energy-per-bit to its floor.
Ideas are proven
in silicon
28nm testchips, probe stations, measured eyes — we finish with measurements, not just papers.