Research Publications
Our comprehensive collection of peer-reviewed publications spanning analog IC design, AI circuits & systems, digital healthcare technologies, and RF communication systems. Explore our contributions to advancing the field through innovative research and breakthrough discoveries.
Publication Statistics
93+
Total Publications
24
Patents
15+
Years Active
4
Research Areas
2025
1 Publication
[95]
A High-Throughput Low-Power SHA-256 Accelerator for Bitcoin Mining in 28nm CMOS Technology
IEEE Journal submitted (2025)
[94]
A Dual-Channel Wearable Ring with MODWT-Based Signal Processing for Non-Invasive Blood Glucose Estimation
IEEE Journal submitted (2025)
[93]
Automated Internal Defect Identification and Localization Based on a Near-Field SAR Millimeter-Wave Imaging System
IEEE Access, vol.13, pp. 24698–24716, DOI: 10.1109/ACCESS.2025.3531913 (2025)
IF: 3.4
SCI
2024
4 Publications
[92]
Analysis and Design of CRC-based SENT Interface for Future Automotive Applications
International SoC Design Conference (ISOCC), pp. 334–335 (2024)
Conference
[91]
A High-Speed HBM Receiver Design for High-Performance Computing Systems
International SoC Design Conference (ISOCC), pp. 47–48 (2024)
Conference
[90]
A Power-Efficient Transmitter Design for 3D-Stacked Memories in 28-nm CMOS Technology
International Conference on Communications and Electronics (ICCE), 2024
Conference
[89]
Bandgap Tuning and Quenching Effects of In(Zn)P@ZnSe@ZnS Quantum Dots
Journal of Powder Materials, vol. 31, no. 3, pp. 226–235 (2024)
SCI
2022
1 Publication
[88]
A Wireless Data Transfer by Using a Patch Antenna for Biomedical Applications
Electronics, vol. 11, no. 24, Article 4197 (2022)
SCIe
2021
3 Publications
[87]
A Smart Wearable Device with Real-Time Control and Collect High Quality of PPG Signal for Smart Healthcare System
MDPI Symmetry-basel, vol. 13, no. 8, pp. 1-9, Oct. 2021
IF: 2.5
SCIe
[86]
A 3-D Reconfigurable Memory I/O Interface Using a Quad-Band Interconnect
IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol.11, no. 5, pp. 832-839, Jan. 2021
IF: 1.6
SCI
[85]
A High-speed Wireless Data Transfer for Non-Destructive Testing
IEEE International SOC Design Conference (ISOCC), Jeju, Korea, 2021
Conference
2020
2 Publications
[84]
A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing
MDPI Electronics, vol. 9, 2020
IF: 2.3
SCIe
[83]
An Energy-Efficient Multi-level RF-Interconnect for Global Network-on-Chip Communication
Analog Integrated Circuits and Signal Processing (AICSP), vol. 102, pp. 1-13, 2020
IF: 0.7
SCI
2019
2 Publications
[82]
A Reconfigurable Biomedical CMOS Power Amplifier Using Adaptive Biasing Technique
Journal of Semiconductor Technology and Science (JSTS), vol. 19, pp. 511-516, 2019
IF: 0.3
SCIe
[81]
Reliability-Aware 3D Clock Distribution Network Using Memristor Ratioed Logic
IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol.10, pp. 1-9, Feb. 2019
IF: 1.6
SCI
2018
6 Publications
[80]
Three-Dimensional Pipeline ADC Utilizing TSV/Design Optimization and Memristor Ratioed Logic
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, pp. 2619 - 2627, Apr. 2018
IF: 1.7
SCI
[79]
A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using Adaptive Frequency Tracking Technique
IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 65, pp.903-907, Jul. 2018
IF: 3.1
SCI
[78]
A High-Speed Mobile Memory I/O Interface using Multi-Modulation Signaling
IET Electronics Letters (EL), vol. 54, Apr. 2018
IF: 1.0
SCI
[77]
An Optimal Design Methodology for Low-Power and Yield-Improved Pipeline ADC
IEEE Transactions on Semiconductor Manufacturing (TSM), vol. 31, pp. 130-135, Jan. 2018
IF: 1.2
SCI
[76]
Design of a Pre-distortion Power Amplifier for Ku-Band/5G applications
IEEE International Conference on Electro Information Technology, 2018
Conference
[75]
A 3D flash ADC structure for high-speed communication applications
IEEE 8th Annual Computing and Communication Workshop and Conference, 2018
Conference
2017
8 Publications
[74]
3-D Power Delivery Network's Subblocks and Regulator Placement Optimized by Evolutionary Algorithm
IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol.8, pp. 1-9, Oct. 2017
IF: 1.6
SCI
[73]
A Low-Power Low-Jitter DLL with a Differential Closed-Loop Duty Cycle Corrector
Analog Integrated Circuits and Signal Processing (AICSP), vol. 90, pp.1-8, 2017
IF: 0.6
SCI
[72]
Yield-Aware Sizing of Pipeline ADC Using a Multi-Objective Evolutionary Algorithm
International Journal of Circuit Theory and Applications (IJCTA), vol. 47, pp. 1-8, 2017
IF: 1.1
SCI
[71]
Resilient Design of Current Steering DACs Using a Transistor Level Approach
Analog Integrated Circuits and Signal Processing (AICSP), vol. 90, pp. 29-41, 2017
IF: 0.6
SCI
[70]
Automatic design and yield enhancement of data converters
Journal of Circuits, Systems, and Computers, vol. 26, no. 1, pp. 1-19, 2017
IF: 0.5
SCIe
[69]
Low-Power and High-Performance 2.4 GHz RF Transmitter for Biomedical Application
IEEE Ubiquitous Computing, Electronics & Mobile Communication Conference, New York City, NY, Sept., 2017
Conference
[68]
A Performance-Aware I/O Interface for 3D Stacked Memory Systems
IEEE Ubiquitous Computing, Electronics & Mobile Communication Conference, New York City, NY, Sept., 2017
Conference
[67]
A Low-Power and Performance-Efficient SAR ADC Design
IEEE International SoC Design Conference, 2017
Conference
[66]
High-Performance RF-Interconnect for 3D Stacked Memory
IEEE International SoC Design Conference, 2017
Conference
2016
7 Publications
[65]
A Near-Threshold Energy-Efficient ASK Transmitter for Biomedical Implants
IEEE Canadian Journal of Electrical and Computer Engineering, vol. 39, no. 4, pp. 292-296, Dec. 2016
IF: 1.1
SCIe
[64]
An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling
IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 63, pp.1-5, Oct. 2016
IF: 3.1
SCI
[63]
A Current-Reused QVCO Using Transformer Feedback Structure
IEEE Microwave and Wireless Components Letters (MWCL), vol. 26, no. 7 pp. 534-536, Jul. 2016
IF: 1.9
SCI
[62]
A Wide Range CMOS Temperature Sensor with Process Variation Compensation for On-Chip Monitoring
IEEE Sensors Journal (SJ), vol. 16, no. 14 pp. 5536-5542, Jul, 2016
IF: 2.5
SCIe
[61]
Design of a Varactor-Based Coupling QVCO Using Bulk-Injection Technique
Analog Integrated Circuits and Signal Processing (AICSP), vol. 86, no. 2, pp.227-232, Jan. 2016
IF: 0.6
SCI
[60]
A 14.4Gb/s/pin 230fJ/b/pin/mm Multi-Level RF-Interconnect for Global Network-on-Chip Communication
IEEE Asian Solid-State Circuits Conference (ASSCC), Toyama, Japan, Nov, 2016. (AR: 35%)
Conference
AR: 35%
[59]
High-speed 3D CMOS Interconnect for Mobile DRAMs
IEEE International SOC Design Conference (ISOCC), Jeju, Korea, Oct. 2016. (Oral)
Conference
Oral
2015
3 Publications
[56]
Design of a Ku-Band Transformer-Based Cross-Coupled Complementary LC-VCO
IET Electronics Letters (EL), vol. 51, no. 11, pp.832-834, May 2015
IF: 1.0
SCI
[55]
A Low-Power 4-PAM transceiver using a Dual-Sampling Technique for Heterogeneous Latency Sensitive Network-on-Chip
IEEE Transactions on Circuits and Systems II (TCAS-II) vol. 62, no. 6, pp. 613-617, Jun. 2015
IF: 3.1
SCI
[54]
Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems
IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA) San Francisco, California, Feb. 2015. (AR: 22%)
Conference
AR: 22%
2014
5 Publications
[53]
A K-Band Divide-by-Five Injection-Locked Frequency Divider Using a Near-Threshold VCO
IEEE Microwave and Wireless Components Letters (MWCL) vol. 24, no. 12, pp. 881-883, Dec. 2014
IF: 1.9
SCI
[52]
An Ultra-Low Power QVCO Using Current-Coupling and Bulk-Injection Techniques
IEEE Microwave and Wireless Components Letters (MWCL) vol. 24, no. 11, pp. 781-783, Nov. 2014
IF: 1.9
SCI
[51]
An Ultra-Low Power Quadrature VCO for 2.4GHz-Band IEEE 802.15.4 Standard
IET Electronics Letters (EL), vol. 50, no. 16, pp.1168-1169, Jul. 2014
IF: 1.0
SCI
[50]
A Dual Positive Feedback Three-Stage Low Noise Amplifier
IEEE Dallas Circuits and Systems Conference (DCAS), Dallas, Texas, Oct. 2014
Conference
[49]
An Energy-Efficient Mobile PAM Memory Interface for Future 3D Stacked Mobile DRAMs
IEEE 15th International Symposium on Quality Electronic Design (ISQED), San Jose, Mar. 2014. (AR: 30%)
Conference
AR: 30%
2013
5 Publications
[47]
A Near-Threshold Charge Pump Circuit using a Dual Feedback Loop
IET Electronics Letters (EL), vol. 49, no. 23, pp. 1436-1438, Nov. 2013
IF: 1.0
SCI
[46]
An Ultra-Low-Power Spike Detector for Implantable Biomedical Systems
IEEE 14th Wireless and Microwave Technology Conference (WAMICON), Orlando, Florida, Apr. 2013
Conference
[45]
An ASK Demodulator for Ultra-Low-Power Implantable Biomedical Microsystems
IEEE 14th Wireless and Microwave Technology Conference (WAMICON), Orlando, Florida, Apr. 2013
Conference
[44]
An Ultra-Low-Power ASK Modulator for Back Telemetry Applications
IEEE 14th Wireless and Microwave Technology Conference (WAMICON), Orlando, Florida, Apr. 2013
Conference
[43]
Reevaluating the Latency Claims of 3D Stacked Memories
Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, Jan. 2013. (AR: 30%)
Conference
AR: 30%
2012
7 Publications
[42]
Utilizing Radio Frequency Interconnect for a Many-DIMM DRAM System
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol 2, no 2, pp. 210-227, Jun. 2012
IF: 2.5
SCIe
[41]
Analysis of Non-Coherent ASK Modulation Based RF-Interconnect for Memory Interface
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol 2, no 2, pp. 200-209, Jun. 2012
IF: 2.5
SCIe
[40]
Structural Optimization of a Thin Film Solar Cell using Numerical Simulation and Design of Experiment Techniques
Journal of Material Science and Technology (JMST), vol 29, no 6, pp. 2557-2563, 2012
IF: 2.8
SCIe
[39]
Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System
ACM Transactions on Architecture and Code Optimization (TACO), vol 8, no. 4, pp. 1-19, Jan. 2012
IF: 0.6
SCIe
[38]
An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling
IEEE Journal of Solid-State Circuits (JSSC), vol 47, no 1, pp. 117-130, Jan. 2012 (Invited)
IF: 4.2
SCI
Invited
[37]
An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simultaneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 50-51, Feb. 2012. (AR: 15%)
Conference
AR: 15%
[36]
Intelligent Scheduling Mobile RF-I for Better Throughput/Watt in a Mobile GPU Memory System
Proceedings of the 7th International Conference on High-Performance and Embedded Architectures and Compliers (HiPEAC), Paris, France, Jan. 2012. (*presenter, AR=25%)
Conference
AR: 25%
2011
5 Publications
[35]
A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and-Off-Chip Interconnects
IEICE Transactions on Electronics, vol. E94-C, no. 5, May 2011
IF: 0.4
SCIe
[34]
Wireline/Wireless RF-Interconnect for Future SoC
IEEE International Symposium on RF Integration Technology, pp. 44-48, Dec. 2011. (Invited)
Conference
Invited
[33]
The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System
IEEE International Conference on Computer Design (ICCD), pp. 388-395, Oct. 2011. (AR: 32%)
Conference
AR: 32%
[32]
RF Interconnect Technology for On-chip and Off-chip Communication
Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), IEICE ED2010-75, pp. 105-108, 2011
Conference
[31]
An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 488-489, Feb. 2011. (AR: 15%)
Conference
AR: 15%
2005
2 Publications
[30]
A 5.0Gbps/Pin Packet-Based DRAM with Low Latency Receiver and Process Insensitive PLL
IEEE Symposium on VLSI Circuits (VLSI) Digest Technical Papers, pp. 50-51, Jun. 2005. (AR: 25%)
Conference
AR: 25%
[29]
A 20GB/s 256MB DRAM with an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 470-471, Feb. 2005. (AR: 15%)
Conference
AR: 15%
2004
2 Publications
[28]
A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme
IEEE Symposium on VLSI Circuits (VLSI) Digest Technical Papers, pp. 36-37, Jun. 2004. (AR: 25%)
Conference
AR: 25%
[27]
1.4 Gbps DLL Using 2nd Order Charge Pumping Scheme for Low Phase/Duty Error for High Speed DRAM Application
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 212-213, Feb. 2004. (AR: 15%)
Conference
AR: 15%
2003
2 Publications
[26]
A 1.2Gb/s/pin Double Data Rate SDRAM with On-Die-Termination
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 1-10, Feb. 2003. (AR: 15%)
Conference
AR: 15%
[25]
A 1.8V 700Mb/s/Pin 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, pp. 1-15, Feb. 2003. (AR: 15%)
Conference
AR: 15%
Patents
24 Patents
[P24]
High-speed Data Buffer for Next-generation DDR7 LR-DIMM Server Applications
Korea Patent, 10-2020-0046649 (2020)
Korea Patent
[P23]
A Data Buffer Design for future High-performance DDR6 LR-DIMM applications
Korea Patent, 10-2020-0046648 (2020)
Korea Patent
[P22]
An low-power clocking interface for future high-speed DDR6/7 applications
Korea Patent, 10-2020-0046647 (2020)
Korea Patent
[P14]
Multi-band interconnect for inter-chip and intra-chip communications
US9178725, 2015
US Patent
[P...]
Additional Patents (20 more patents not fully listed)
Various patent offices and years
Multiple Patents