We carve intelligence
into silicon
From neural accelerators to hybrid NPUs — we build AI directly in digital circuits.
The NPU's heart —
thousands multiply at once
The MAC array — a systolic grid where thousands of multiply-accumulators beat on one clock.
Performance is decided
by flow, not math
Where weights stay and how data streams — dataflow decides half of your power budget.
Inference on-chip,
right at the biosignal
ECG and PPG are answered before they leave the chip — an always-on bio-AI accelerator.
Designed, laid out,
and made real
RTL to layout to chip — our accelerator has already passed GDS into real silicon.
Flexibility and speed
on one die
CPU generality fused with NPU horsepower — the workload changes, the chip doesn't.
Picojoules
per inference
Think energy, not power — shaving picojoules per inference is everything at the edge.
The CPU core
conducts it all
A RISC pipeline from fetch to write-back — even in the accelerator era, the CPU conducts.
Compute is fast,
data is late
The memory wall — HBM bandwidth and CXL links keep thousands of MACs fed without stalls.
We speak in measurements,
not simulations
Silicon running on a test board, measured TOPS/W — behind every paper, a real chip.