Capstone Design · Topic 01 · Beginner Track

CD — Clock Driver

DDR5 Memory Module Signal Buffer · RDIMM / LRDIMM

Design a CD (Clock Driver) — the chip sitting between the CPU and multiple DRAM chips on a DDR5 server memory module. Work through four structured phases: VerilogA behavioral model → Analog block schematic (PLL, TX, RX, BGR) → Layout + PEX extraction → Full-chip All-PVT verification using Ocean script.

4 Design Phases Cadence Virtuoso Razavi Reference 🎓 Beginner Level

>9600 MT/sTarget Data Rate

Phase 1VerilogA Model

Phase 2Analog Schematics

Phase 3Layout + PEX

Phase 4All-PVT Ocean

PLLLow-Jitter Clock

DFE 8-tapCA Receiver

RazaviTextbook Reference

>9600 MT/sTarget Data Rate

Phase 1VerilogA Model

Phase 2Analog Schematics

Phase 3Layout + PEX

Phase 4All-PVT Ocean

PLLLow-Jitter Clock

DFE 8-tapCA Receiver

RazaviTextbook Reference

CD Architecture — Reference Slides

Use these diagrams throughout all four design phases. Each slide maps to a specific block you will design.

Big Picture — Read This First

What Is a CD (Clock Driver)?

Beginner Understand the system before designing a single transistor.

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The CD is a Signal Amplifier

Think of it like a speaker amplifier: the CPU sends one weak signal, the CD re-drives it strongly to 8–18 DRAM chips simultaneously — just like an amp driving multiple speakers from one source input.

Analog Buffer

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The Fan-Out Problem

Without a CD, the CPU drives all DRAM chips directly. Each chip adds ~0.5 pF. At 9600 MT/s the RC time constant collapses the eye. The CD isolates the load — the CPU only sees one chip input.

Load Reduction

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Three Main Blocks Inside

① PLL — multiplies reference clock → low-jitter DRAM clocks. ② CA Receiver + DFE — receives address/command bus, removes ISI. ③ CA Driver — re-drives clean signals to DRAM ranks.

System Architecture

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PODL — Zero Static Power

DDR5 changed the CA bus from SSTL (biased at VDD/2, always drawing current) to PODL (Pseudo Open Drain — parks at VDD, zero DC current when idle). Direct application of Circuit Theory: knowing when a signal dissipates power.

Power Design

Capstone Design Guide

CD Project — 4 Design Phases

Each phase builds on the previous. By Phase 4 you will have a full-chip, All-PVT verified CD top.

Phase 1

VerilogA Behavioral Model

System-level simulation · Top-down design

Phase 2

Analog Block Schematics

PLL · TX · RX · BGR — Razavi

Phase 3

Layout + PEX Extraction

Real silicon parasitics · DRC · LVS

Phase 4

All-PVT Verification

Ocean script · Full-chip · SS/TT/FF corners

Phase 1 · VerilogA

Build a Behavioral Model of the Entire CD

Before drawing a single transistor, model the CD's behavior in VerilogA (Cadence Spectre). This lets you verify the system specification — correct fan-out, correct timing, correct output levels — in minutes rather than hours.

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Why VerilogA first? A behavioral model runs 100× faster than a transistor-level simulation. Catch architecture mistakes (wrong polarity, wrong timing) before committing to transistor design. Professors call this top-down design.

What to Build

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CD Top-Level VerilogA Module

Model the CD as a black box: CK_in→PLL→CK_out[0..7] and CA_in[6:0]→QACA[13:0]. Use ideal delay and voltage swing.

Cadence Virtuoso

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Timing Diagram Verification

Run transient simulation at 4800 MT/s. Check: ① setup/hold on CA. ② Clock-to-Q delay ≤ spec. ③ Output swing reaches VDD (PODL high = logic 1).

Spectre / ADE

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Specification Table

One-page spec: signal names, direction, voltage level (PODL vs CMOS), fan-out count, max data rate, and power budget per block. Professor sign-off required before Phase 2.

Excel / Sheets

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New to VerilogA? Start with a 2-input inverter module. Key syntax: @(cross(V(in)-0.5*vdd, +1)) detects a rising edge. Your lab notes will cover this — also see Cadence Learning Center "VerilogA for Behavioral Modeling".

Razavi — Chapters to Read for Phase 1

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Razavi — Design of Analog CMOS Integrated Circuits (2nd Ed.)

System-level understanding before transistor design

Ch. 1

Introduction — Noise Margin, Fan-out, Signal Integrity

Why analog matters in "digital" chips. VDD levels, logic thresholds, and power consumption P = αCVDD²f. Directly explains why the CD needs careful analog design even though it's a buffer chip.

→ Use this to justify your spec table: noise margin budget, power budget per block

Ch. 2

Basic MOS Device Physics — gm, ro, VGS, VDS

Triode vs saturation, gm = 2ID/VOD, ro = VA/ID. Every transistor in the PLL, TX, and RX operates in one of these regions. You'll use these equations when sizing transistors in Phase 2.

→ Review before starting Phase 2 schematic entry

Ch. 3

Single-Stage Amplifiers — CS, CG, Source Follower

Common-source gain = −gm·RD, output impedance, bandwidth. The CD's CA receiver uses a source follower input stage. The clock output driver is a CS stage with large W/L for high current drive.

→ Phase 2 preview: RX input stage and TX output driver come from here

Online Resources — Beginner Level

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DDR5 RDIMM Architecture (YouTube)

Search "DDR5 RDIMM architecture explained" — focus on: where is the RCD/CD chip on the module? How does it connect to CPU and DRAM?

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JEDEC DDR5 Overview (Free PDF)

JEDEC.org free DDR5 whitepaper — find the RCD block diagram. This is exactly what you model in VerilogA.
jedec.org →

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Cadence VerilogA Tutorial

Cadence Learning Center — free "VerilogA for Behavioral Modeling" module. Covers the @(cross()) syntax you need.
cadence.com →

Phase 1 Checklist

Read Razavi Ch.1–3. Write one paragraph per chapter: how does it apply to the CD chip?

Draw the CD system block diagram: CPU → CA[6:0] → CD → QACA[13:0] × 2 sub-channels → DRAM. Label every signal name and direction.

Write the VerilogA top module in Cadence Virtuoso using @(cross()) events to model signal propagation with ideal delay.

Run transient sim at 4800 MT/s. Verify CA timing matches the JEDEC spec figure — show to professor.

Fill in the specification table and get professor sign-off before moving to Phase 2.

Phase 2 · Schematic Design

Design Each Analog Block at Transistor Level

Build each CD sub-block as a real CMOS schematic in Cadence Virtuoso. Reference Razavi for every topology. Four key blocks: PLL, TX Driver, RX (with DFE), and BGR (Bandgap Reference for bias).

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Phase 2 requires Phase 1 complete. Use your VerilogA waveforms as the target spec for each block. Every transistor schematic must reproduce the ideal VerilogA behavior within 10% tolerance on timing and swing.

Block 1 — PLL (Phase-Locked Loop)

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What the PLL does

Takes the CPU reference clock (e.g. 800 MHz) and outputs 8 low-jitter DRAM clock pairs. Loop equation:

f_out = N × f_ref / M

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Blocks to design in Cadence

① PFD — XOR / D-FF phase-frequency detector
② Charge Pump — matched UP/DN current sources
③ Loop Filter — passive RC (from Circuit Theory)
④ VCO — 5-stage ring oscillator (beginner) or LC
⑤ Divider — flip-flop chain

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Razavi — PLL Design

Read before drawing the PLL schematic

Ch. 15

Oscillator Design (VCO)

Ring oscillator: N inverter stages, f = 1/(2N·td). For beginner CD project a 5-stage CMOS ring VCO is recommended — simpler to design and characterize. Tune frequency by changing W/L of inverter PMOS/NMOS.

→ Design and size the VCO first. Run frequency vs. VDD sweep to verify tuning range covers the target.

Ch. 16

Phase-Locked Loops — Complete PLL Design

PFD, charge pump, loop filter design (ωn, ζ from loop equations), PLL locking behavior. Lock time, jitter transfer function, phase noise. PLL loop bandwidth ≈ f_ref / 10 is a good starting point.

→ Core chapter. Work every derivation. Verify lock in simulation: transient shows VCO frequency pulling toward f_ref within 2 µs.

Ch. 11

Bandgap Reference (BGR)

PTAT + CTAT combine to give a temperature-independent ~1.25 V reference. The CD uses BGR to supply stable VREF to all internal bias circuits across −40°C to +125°C.

→ Design a self-biased BGR. Simulate VREF vs temperature — variation should be <5 mV over the full range.

Block 2 — TX Driver (Clock Output)

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CMOS Push-Pull Output Driver

Large W/L PMOS + NMOS pair. Must deliver full voltage swing into 50 Ω (DDR5 PODL termination) with rise/fall time <50 ps — that's within one UI at 9600 MT/s (UI = 104 ps).

Razavi Ch.3 — CS Amp

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ZQ Impedance Calibration

Tune driver impedance to match PCB trace (40/48/60 Ω). Use a resistor-ladder comparator circuit with binary search. Razavi Ch.13 covers the comparator you need.

Razavi Ch.13 — Comparator

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FFE Pre-Emphasis (Optional)

Boost the first edge of each bit transition to compensate for PCB trace RC roll-off. For beginner level, skip FFE and verify the eye is open without it — add FFE in Intermediate track.

Intermediate Track

Block 3 — RX Receiver (CA Bus Input + DFE)

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Razavi — RX / Differential Amplifier / Comparator

The CA receiver = diff-pair + StrongARM slicer

Ch. 4

Differential Pairs — Input Stage of RX

NMOS diff-pair with tail current source. Differential gain Ad = gm·RD. CMRR = Ad/Acm. The CD's CA receiver samples the incoming CA bus with VIN+ (signal) and VIN− (VREF). Size the tail current so bandwidth >5 GHz.

→ Design the diff-pair input stage first. Simulate gain, bandwidth, and CMRR.

Ch. 5

Current Mirrors — Bias Circuits for RX

Simple, cascode, Wilson mirrors. The RX tail current source is a PMOS current mirror fed from the BGR. Use a cascode mirror for better output impedance (less gain error and offset).

→ Design the RX bias circuit. Verify tail current matches the spec even when VDD varies ±10%.

Ch. 13

Comparator — DFE Bit Slicer

StrongARM latch comparator: regenerative latch gives fast decision (<100 ps). The DFE slicer in the CA receiver is essentially a comparator deciding 0 or 1 for each incoming bit at 9600 MT/s.

→ Implement the bit-slicer as a StrongARM latch. Measure offset voltage (aim for <5 mV).

Phase 2 Deliverables Checklist

PLL schematic: PFD + Charge Pump + Loop Filter + Ring VCO + Divider. Verify lock <2 µs, jitter <20 ps RMS at TT/25°C.

TX Driver schematic: CMOS push-pull. Verify swing = VDD, rise/fall <50 ps into 50 Ω load.

RX Receiver schematic: diff-pair + StrongARM slicer. Measure sensitivity <50 mV, offset <5 mV.

BGR schematic: self-biased bandgap. Simulate VREF vs temperature (−40°C to +125°C) — variation <5 mV.

Top-level testbench: connect all blocks, run a system transient showing CA data flowing CPU → RX → re-timer → TX → DRAM input.

Phase 3 · Layout + PEX

Draw Physical Layout — Extract Real Parasitic R and C

Schematic uses ideal wires. Real silicon has parasitic R and C in every wire and contact. Draw the layout in Cadence Virtuoso Layout, then run PEX (Parasitic Extraction) to get actual silicon performance.

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Common beginner mistake: Running only pre-layout (schematic) simulation and calling it done. Parasitic capacitance on clock wires can add 20–50 ps of extra delay and 30% more jitter. You must run PEX to know if the design meets spec on real silicon.

Layout Rules Per Block

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PLL — Common-Centroid Matching

Charge pump UP/DN current sources must be laid out symmetrically (common-centroid) to minimize systematic offset. Any mismatch causes static phase error (dead zone). Use interdigitated PMOS pairs.

Common-Centroid

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TX Driver — Multi-Finger FET

Large W/L PMOS/NMOS: use multi-finger layout (finger width ≤ 2 µm to reduce gate resistance). Route output metal wide to minimize output resistance. Run DRC clean after each block.

Multi-Finger FET

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RX + Slicer — Guard Ring

Diff-pair: common-centroid to cancel gradient mismatch. Shield the RX input with a P+ guard ring to reduce substrate noise coupling. Keep signal lines short and differential.

Guard Ring · LVS

PEX Flow — Step by Step

Draw layout in Virtuoso Layout Suite. Follow PDK DRC rules. No violations allowed before extraction.

Run DRC (Design Rule Check): zero errors required. Common errors: minimum spacing, minimum width, well enclosure violations.

Run LVS (Layout vs. Schematic): layout netlist must exactly match your Phase 2 schematic. Fix any missing connections or wrong device sizes.

Run PEX using Calibre xRC or Cadence QRC. Extract R+C parasitic netlist — this tells you how much resistance and capacitance each wire adds.

Post-layout simulation: load extracted netlist into Spectre ADE. Re-run Phase 2 testbenches. Document pre-layout vs post-layout timing degradation.

If post-layout timing fails: identify the critical path (worst parasitics) and iterate the layout — widen wires, shorten routes, add buffer stages.

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What is PEX? After drawing the physical layout, the EDA tool (Calibre or QRC) looks at every metal wire, contact, and via. It calculates: ① How much resistance does this wire have? ② How much capacitance between adjacent wires? It adds these as extra R/C elements to your netlist — so the re-simulation behaves exactly as real silicon would.

Layout Resources — Beginner

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Cadence Virtuoso Layout Basics

Search "Cadence Virtuoso layout tutorial beginner" on YouTube. Many free videos show MOSFET layout from scratch, plus DRC/LVS workflow.

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Common-Centroid Matching Notes

Search "common centroid layout CMOS analog" — CMC (Canadian Microelectronics) has free lecture notes essential for matching the charge pump current sources.

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Razavi Ch.18 — Layout Guidelines

Contains guard rings, metal shielding, device matching techniques — all directly applicable to the CD layout. Read before starting the PLL layout.

Phase 4 · Ocean Script · All-PVT

Full-Chip Verification — All Process, Voltage, Temperature Corners

A chip that works at 25°C / nominal voltage / typical process is not enough. Real silicon must work across all manufacturing variations and field conditions. Phase 4 automates this verification using Ocean scripts in Cadence Spectre.

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What is PVT? Process (SS / TT / FF — Slow-Slow / Typical / Fast-Fast from the fab) × Voltage (VDD −10% / nom / +10%) × Temperature (−40°C / 25°C / 125°C) = 27 combinations minimum. Ocean script runs all 27 automatically overnight.

All-PVT Simulation Matrix

Corner	Process	VDD	Temp	Why Critical?
SS / Low-V / Hot	Slow-Slow	0.99 V (−10%)	+125°C	Slowest transistors + highest leakage → worst timing. If it passes here, it passes everywhere.
FF / High-V / Cold	Fast-Fast	1.21 V (+10%)	−40°C	Fastest transistors → may violate hold time or cause output overshoot.
TT / Nom / 25°C	Typical	1.1 V	25°C	Nominal design point — baseline for comparison with all other corners.
SF / FS Corners	Slow-N / Fast-P	Nominal	25°C	NMOS and PMOS have different speeds → imbalanced rise/fall times.

Ocean Script — Automation Tool

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Ocean = Cadence Spectre's scripting language for simulation automation.
Instead of clicking through the ADE GUI 27 times, write a script that loops over all PVT corners automatically. Key functions: simulator('spectre'), analysis('tran' ?stop 1u), envOption('temperature 125), save('PLL_out 'v), run(). Ask your professor for the lab Ocean script template.

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PLL — All-PVT Verification

Verify PLL locks at every corner. Key metric: Lock Time ≤ 10 µs and Jitter ≤ 20 ps RMS at SS/Low/Hot (worst case). If it fails, widen the loop filter or increase charge pump current.

Ocean .pvt loop

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TX Driver — Eye Diagram All Corners

Eye Diagram must be open (height >100 mV, width >0.3 UI) even at SS/Low/Hot. If the eye closes, increase driver W/L or add pre-emphasis (FFE).

Eye Diagram

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RX + BGR — Offset All Corners

Verify RX input offset stays <10 mV at all PVT corners. Verify BGR VREF variation <5 mV across −40°C to +125°C. If offset is large, add auto-zeroing or calibration.

Offset / Sensitivity

CD Top Full-Chip Checklist

Assemble CD top schematic: instantiate PLL, TX (×8 clock outputs), RX (CA receiver), BGR, FSM controller as sub-cells in a top-level schematic cell.

Write the Ocean script: loop over all PVT corners (minimum: SS/LL/125, TT/TT/25, FF/HH/−40). Auto-save waveforms to a results directory.

Run full-chip transient: apply walking-1 or PRBS-7 CA test pattern to CD top. Verify all 14 QACA outputs are correct at every PVT corner.

Create summary table: for each PVT corner record: PLL lock time, jitter, TX rise/fall, Eye height/width, RX offset. Mark PASS/FAIL vs JEDEC spec.

Prepare capstone presentation: 8–10 slides covering — Problem/Motivation, System Architecture, Each Block Design, Pre-layout vs Post-layout comparison, All-PVT results table, Conclusion. Include Eye Diagram at TT/25°C and SS/Hot corners.

Razavi — Background for Phase 4

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Razavi — Why Circuits Change with PVT

Understanding the root cause of corner variation

Ch. 7

Noise in MOSFET Circuits

Thermal noise (4kTγgm) and flicker noise (Kf/CoxWLf). Noise in the PLL VCO and charge pump directly contributes to output jitter. This is why jitter increases at the SS/Hot corner — both mobility decreases and noise increases with temperature.

→ Use this in your final presentation to explain why jitter is worst at SS/Hot.

Ch. 17

Short-Channel Effects & Technology Scaling

DIBL, velocity saturation, channel-length modulation — these effects are stronger at advanced nodes (7nm, 5nm) and change transistor behavior between TT and SS/FF corners more than older nodes.

→ Explains why PVT corners behave differently — not just scaled versions of each other but qualitatively different transistor physics.

What You're Designing

CD Internal Blocks — Six Sub-Cells

Each block is a separate Cadence cell. Design in Phase 2, lay out in Phase 3, verify all together in Phase 4.

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PLL — Phase-Locked Loop

Receives CPU reference clock. Outputs 8 low-jitter DRAM clock pairs. Razavi Ch.15–16. Key specs: Lock <10 µs, Jitter <20 ps RMS, BW ≈ f_ref/10.

Razavi Ch.15–16

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TX Driver — Clock & CA Output

CMOS push-pull with ZQ calibration. Drives 50 Ω PODL load. Rise/fall <50 ps, output impedance 40–60 Ω, swing = VDD. Razavi Ch.3.

Razavi Ch.3

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RX Receiver — CA Bus Input

Diff-pair input + StrongARM slicer. Samples CA[6:0] at 9600 MT/s. Sensitivity <50 mV, offset <5 mV, BW >5 GHz. Razavi Ch.4 & Ch.13.

Razavi Ch.4, 13

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BGR — Bandgap Reference

Temperature-stable ~1.25 V bias reference. Supplies VREF to all bias circuits. VREF variation <5 mV from −40°C to +125°C. Razavi Ch.11.

Razavi Ch.11

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FSM — Digital Controller

Verilog FSM: receives I2C/I3C commands → controls PLL mode, ZQ calibration, parity check, ALERT_n assertion. Simulate in ModelSim or Vivado. 4 states: IDLE → RX → EXECUTE → DONE.

Verilog / ModelSim

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CD Top — Full-Chip Integration

All blocks instantiated as sub-cells with power routing (VDD/VSS rails, decoupling caps). Phase 4: Ocean script runs All-PVT on the assembled CD top and generates the PASS/FAIL report.

Ocean / All-PVT

Explore Other Topics

All Six Capstone Topics

Each topic follows the same four-phase design flow. Click to explore.

Topic 02

DB — Data Buffer

LRDIMM bidirectional DQ/DQS buffer

Topic 03

BIST — Self-Test Engine

On-chip PRBS test, replaces ATE

Topic 04

D2D — Die-to-Die Link

18 / 36 Gb/s chiplet interface

Topic 05

PHY — Physical Layer IP

LPDDR6 14.4 Gb/s · ISSCC 2026

Topic 06

HBM — High-BW Memory

AI accelerator >1 TB/s interface

Start Your CD Capstone Project

Ask your professor for the Cadence PDK, VerilogA template, and Ocean script template to begin Phase 1. All four phases are designed to be completed in one semester.

Back to Capstone Topics Ask Professor